The course builds on the Digital Systems class and provides an in-depth analysis of digital design and computer architecture. Core topics include Finite State Machine (FSM) controllers and pipeline design using Hardware Description Language (HDL). Students will: design and analyze combinational and sequential circuits; perform timing analysis; design and implement Finite State Machine(FSM) controllers and next-state decoders; Identify a single-cycle processor; Identify, design, and implement a pipelined processor; explain cache and virtual memories. Prerequisite: ECE 263 Corequisite: ECE 361